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Advanced Routing Automation
Solves Today's Layout Challenges

Technical Advisory Board


Mark McDermott is principal and general partner in the Silicon Web Group and an adjunct assistant professor at the University of Texas. Mark received his MSEE from the University of Texas and has since co-founded six companies, led engineering teams in the development of PowerPC processors and Intel x86 processors, and been granted 19 patents in microprocessor design and test. He has served as CEO of DynaFlow Computing, VP engineering and co-founder of Somerset Embedded Technologies, VP engineering and co-founder of VisionFlow, general manager and director of the Texas Development Center for Intel Corporation, director of the PowerPC Somerset Design Center, and director of the Austin Design Center for Cyrix.


David Z. Pan is assistant professor and director of the University of Texas Design Automation Laboratory in Austin. He received his Ph.D. in computer science from UCLA. Before going to UT, he was a research staff member at the IBM T. J. Watson Research Center. His research interests include nanometer physical CAD, design for manufacturability (DFM), variation-tolerant designs, novel circuitry and CAD for low power, and vertical integration of architecture, circuit and technology. He has served in the program committees of many major conferences, including ICCAD, DATE, ASPDAC, ISPD, ISQED, and ISCAS. He has received numerous awards, including the SRC Inventor Recognition Award in 2000 and the IBM Faculty Award in 2004 and 2005.


Riko Radojcic is a consultant to semiconductor and EDA companies who specializes in the integration of semiconductor process and design considerations. Riko received his PhD from University of Salford, UK, and has more than 20 years of experience in the semiconductor industry. He served in management roles for PDF Solutions, Tality and Cadence, specializing in design technology integration and process characterization and modeling. He has also held management and engineering positions with Unisys, Burroughs, and Ferranti Electronics.



Naveed Sherwani, PhD., has over 19 years experience in technical engineering and general management. Prior to founding Open-Silicon, he was the founder and general manager of Intel Microelectronics Services, where he led efforts to promote the use of disciplined ASIC methodologies to improve design efficiency and time-to-market. Naveed co-architected the Intel microprocessor design methodology and environment that has been used in various leading microprocessors. Naveed has served as a professor at Western Michigan University, where his research concentrated on VLSI Physical Design Automation, combinatorics, and graph algorithms. Naveed is the author of the main textbook on physical design, which is widely used at major universities around the world. In addition, he has authored or co-authored various books and articles on physical design automation and ASICs and has been a frequent speaker at international technical conferences around the world. Naveed received his PhD from the University of Nebraska-Lincoln.