Industry Challenge

As the semiconductor industry migrates from 65nm process technologies to 45nm and below there is a sharp increase in the interactions between design layout and the silicon process used to manufacture the design. These interactions, known as design-based yield limiters, result in lower chip performance, higher manufacturing costs and lower overall chip yield. Design-based yield limiters can not be simply removed by product engineers working in a fab. They are chip layout specific and must be "designed out" from the very beginning. Without a fundamental change in design methodology that addresses design-based yield limiters, IC design risk is expected to increase, causing slower performing chips, loss of market window and reduced profitability.

Pyxis NexusRoute

NexusRoute is a yield-aware, IC router targeted at high performance designs manufactured in complex < 65nm processes. NexusRoute simultaneously optimizes a design for faster performance, lower power and higher yield. Unlike conventional physical design tools which use multiple iterative approaches that try to locally optimize a design, NexusRoute employs a new routing architecture and one-pass flow where timing, power and yield are simultaneously optimized during global and detailed routing resulting in superior routability, performance, power and yield.

The NexusRoute architecture provides an enabling technology for emerging nanometer silicon process technologies by bringing manufacturing knowledge earlier into the design flow to create a correct-by-construction layout. Utilizing advanced DFM-aware algorithms with accurate process models for random, systematic and parametric yield limiters, NexusRoute selectively spreads and widens wires to improve performance and power while simultaneously reducing yield limiters in the design. By using a correct-by-construction approach NexusRoute reduces the need for post-layout DFM iterations that can cause timing problems for high performance designs.

NexusRoute is a full IC routing solution that takes as input a placed design and outputs a fully optimized routed database. NexusRoute has been designed to easily augment existing EDA design flows by using industry standard interface formats such as LEF, DEF, Verilog, SDCs, Liberty and SPEF to exchange design data with the rest of the flow. NexusRoute also uses application programming interfaces (APIs) to interact with third party analysis tools and models for timing, signal integrity, power, manufacturability and yield.

Example NexusRoute Flow Integration with
Magma, Synopsys & Mentor Tools

NexusRoute supports a wide variety of advanced design rules (both hard and preferred rules) along with a comprehensive analysis environment including links to signoff timing, signal integrity, power and yield analysis to steer the design optimization process. NexusRoute reduces design risk earlier in the project, accelerates time to tape-out regardless of chip size, reduces the risk of silicon re-spins and accelerates time-to-volume all while maintaining or improving IC performance and power.

Pyxis Professional Services

Pyxis Technology, Inc. has a seasoned team of design, manufacturing and EDA veterans representing hundreds of man years of experience in the design and manufacturing of advanced microprocessor and ASIC designs. Pyxis Professional Services leverages this unique combination of design and manufacturing knowledge to help designers tackle the emerging design challenges of nanometer technology integrated circuits. Pyxis also has strong relationships with key design-for-manufacturing solutions providers such as Brion Technologies, PDF Solutions, and Ponte Solutions and will work with you to determine a design-for-yield methodology that best fits your overall design style and goals.

• Faster Performance, Lower Power & Higher Yield
• Yield & Performance Driven IC Routing Platform Architected for <65nm designs
• Reduces Design & Manufacturing Cycle up to 4X
• Easy Design Flow Integration

• Yield-Aware Block or Chip Routing Service
• Increase Design Margins, Lower Power & Increase Yield

• DFM Design Rule & Flow Assessment

• Routability & DFM Quality Library Assessment