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Advanced Routing Automation
Solves Today's Layout Challenges

Pyxis News:

2010

Jun 11 -- Press Release
Pyxis Router Selected for TSMC 28nm Analog/Mixed-Signal Reference Flow

Jun 9 -- EDACafe
Ciranova Helix Selected in TSMC Analog Mixed-Signal Reference Flow 1.0 for Physical Design Automation

Jun 8 -- Daniel Nenni
TSMC Unveils First Ever AMS Reference Flow!

Jun 8 -- PR Newswire
TSMC Unveils Two New Reference Flows

Jun 7 -- SOCcentral
Controllable Automation and Interoperability Standards


2009

Sep 30 -- Press Release
Pyxis Technology Continues Growth, Achieves Funding Milestone

Jul 28 -- Chip Design
Laker, OA, Pyxis - A happy and expanding IC family

Jul 27-30
See the Pyxis NexusRoute Automated Custom Routing Solution in Four Partner Booths at DAC 2009

Jun 15 -- Chip Design
More Automation is Needed in Custom Layout Design

Apr 7 -- Press Release
Pyxis Technology Raises $3.0M in Expansion Capital


TSMC Selects Pyxis Router for 28nm AMS Reference Flow 1.0

"The addition of the Pyxis router to our AMS reference flow brings a entirely new level of automation to our customers who are doing complex analog and mixed-signal designs."

Tom Quan
Deputy Director of Design Methodology
and Service Marketing at TSMC

At Pyxis Technology, our mission is to provide integrated circuit (IC) designers and foundries with the advanced software solutions needed to complete the physical design and routing of custom circuits (Analog and Digital) and system-on-chip (SoC) designs.

Physical Design Challenges
Design requirements and economies of scale are driving the need to combine custom analog circuits together with millions of digital logic gates onto mixed-signal chips. Design teams trying to combine interactive custom routers with various automated place and route tools find poor interoperability and tools that often produce conflicting results. Even for purely digital SoC designs, capacity and the complexity of process design rules can choke the analysis engines of traditional automatic place and route tools. Additionally, critical paths in nanoscale SoC layouts with process geometries of 45nm and smaller, are sometimes best resolved by making custom digital circuit changes. Since 2005, average custom layout content has increased to 25% of chip area. Custom design and layout is becoming a gating factor in the design of integrated circuits.

To address today’s IC routing challenges, designers need both hands-on control to handle custom design performance and high-speed routing automation to deal with design capacity.

Pyxis Technology Solutions
Pyxis Technology provides advanced routing engines specifically designed to handle the complexities and capacity of nanoscale IC designs. Built on the OpenAccess (OA) database, Pyxis routing solutions are seamlessly interoperable with other physical design tools to create a best-in-class physical design flow working in concert. Pyxis Technology enables assisted custom design automation with integrated analysis for a true "what-if" exploration of custom analog and digital design, and fast, high-capacity automated routing to complete the SoC layout.

NexusRoute-HPC : Automated Routing for High-Performance Custom Design
The Pyxis Technology NexusRoute-HPC product is a custom layout solution that optimizes the routing of advanced analog and mixed-signal designs. NexusRoute-HPC delivers orders of magnitude faster routing speed and analysis for high-performance custom designs.

Combined with design layout and placement tools, the Pyxis NexusRoute-HPC tool provides powerful all-level hierarchical routing without abstracts, leading to the improved performance and compaction of custom IC designs. NexusRoute-HPC also includes built-in design rule checking, parasitic extraction, and timing analysis capabilities for design optimization.

NexusRoute-SoC : High-speed, High-Capacity Routing for Nanoscale SoC
Pyxis Technology’s NexusRoute-SoC uses a new patent-pending architecture and a one-pass flow to perform correct-by-construction optimization of IC performance, power and yield during routing of nanoscale SoC designs. SoC designers have seen 4X performance improvements in design closure cycle times using Pyxis routing technology.

Specifically designed to handle high-capacity designs, the NexusRoute-SoC tool is tuned to handle the complexity of design process rules of nanoscale processes. The tool delivers blazing routing runtime performance while simultaneously checking design rules and optimizing the SoC design for timing, signal integrity, power and yield. NexusRoute-SoC provides capacity to handle multi-million-gate SoC designs, and supports multi-threaded and distributed operations for even shorter routing runtimes.

Pyxis Tool Interoperability
NexusRoute-HPC and NexusRoute-SoC are fully integrated with common IC layout flows. The Pyxis tools provide full interoperability with the OpenAccess database and standard file formats. Interoperability ensures a seamless interaction between layout editor and the Pyxis router with no need to export and import data between different vendor tools in the custom design flow.

Leading electronics original equipment manufacturers (OEMs) have installed Pyxis NexusRoute tools into their IC layout flows and have achieved successful tapeouts on major designs.